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- En octo. 2003
[ST Microelectronics]
Cadre CDI
• Experience on project management and coordination between multi-site teams.
• Experience in RTL coding (VHDL/Verilog), design verification, synthesis, testability insertion (DFT).
• Experience in STA (Static Timing Analysis)
• Experience in layout verification (DRC, LVS with Mentor Calibre and PetR tools encounter, Astro and Iccompiler)
• Expertise in “RTL to layout“ ASIC implementation flow (CADENCE, and SYNOPSYS backend flows)
• Expertise in scripting with tcl, tcltk and shell for “RTL to layout” flow automation.
• Knowledge on “Low power techniques” on BackEnd Flow (switches, retention cells)
• Expertise with “code sharing system” CVS in unix/linux platforms.
• Good documentation and communication abilities on French and English languages.
• Good team player and high ability to work under challenging schedules
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