- [Computer Science]
Feb. 2005 - King Fahd University of Petroleum and Minerals, Present Dhahran , Saudi Arabia Assistant Professor at the Computer Engineering Department, College of Computer Science and Engineering. Teaching: Taught the following courses: · COE-200 Fundamentals of Computer Engineering · COE-205 Computer Organization and Assembly Language · COE-308 Computer Architecture · COE-485 Senior Project Design · COE-390 Seminar · COE-400 Digital Systems Design · Initiated several educational projects in embedded systems, digital systems and FPGA-based systems. · Senior Design Projects: Stair-climbing robot PC-controlled, directional WiFi camera Appointment reminder SMS messaging system Automated school pick up system Hardware-based secure payment system WiFi Remote Controlled vehicle Course Evaluation Average of: 8.2/10. Research: Intensive Research/Development Program in SoC Design and Embedded Systems: · Developed a research activity on networks-on-chips and in the process of building a methodology and its toolset for the design of networks-on-chips. · Involved in System-on-Chip (SoC) design and embedded systems, more precisely in hardware/software co-design/co-verification · Involved in high speed AES encryption engine development (500 Gbits/s). Completed synthesizable RTL verilog code fully verified and synthesized. · Interests in robotics: robot locomotion, navigation, swarm of robots · Interests in Computer Architecture, more precisely in massively parallel SoCs. Research Grants : · SABIC/Fast Track Grant entitled : "Using the On-Chip Advantage in Designing Networks -on-Chips", 75,000 SAR = USD $20,000. Pricipal Investigator · KFUPM Grant entitled : "Developing A Network-on-Chip for FPGAs", 150,000 SAR = USD $40,000. Co-investigator · KFUPM Grant entitled : " The Design and Simulation of a Multi-core Vector Processor", 200,000 SAR = USD $53,400. Co-investigator Reviewer for the following conferences: IEEE-GCC, SOCC2007, DELTA-08 and others

- En janv. 2004 [Lambda Opticalsystems Corporation] CDI
­ Lambda Opticalsystems Corporation ,

- En déce. 2004 [Director Systems Integration and Testing] CDI
Reston , VA, USA Director Systems Integration and Testing · Responsible for developing the testcases and regression suite · Qualification of the software release on the hardware revisions. · Evaluation of performances for protection when incident · Testing of the control plane. Redundancy and Switchover cases.

- En octo. 2001 CDI
Zarlink Semiconductor,

- En déce. 2003 [Senior ASIC Designer and Chip] CDI
Ottawa , ON, Canada Senior ASIC Designer and Chip Architect Involved in several projects · 16kx16k channels TDM switch project: Responsible for the verification and wrap-up design. Technical expert on the side of the RTL group dealing with the implementation group. Development of the verification test suite Code coverage Regression and Gate level simulation Timing closure · VDSL project: Responsible for the design of the Ethernet over VDSL (EoVDSL) adaptation layer block. Developed a simulator to simulate the behavior of the EoVDSL layer under several conditions. Simulator developed in C. Generates industry standard waveform .vcd files. Responsible for defining the architecture of a multi-channel VDSL chip. o Invented a new improved method to instantly compute variable packet fragment sizes to scale the fragments according to each channel data rate in order to avoid skew between fragments. A patent application has been written but has not been filed. o Proposed several schemes to realize the interconnection of two family of chips using either point to point parallel interfaces or point to multi-point ones in order to reduce the pin count. · ATM AAL2 Switch: Responsible for the top level verification Developed a high level language to describe testcases using non- deterministic methods like random number generators. Merged two block level testbenches to realize the top level testbench. Wrote several Perl scripts and C/PLI functions to realize the integration of the testbench component in both the block level and the top level testbenches. June 2000 - Applied Micro- Circuits Corporation ,

- En octo. 2001 [Senior ASIC Design and Verification] CDI
Ottawa , ON, Canada Senior ASIC Design and Verification Engineer Involved in several projects · Hudson 2: OC192 (10 Gbps) G.709 Forward Error Correction Unit (Respin of Hudson 1) Main verification resource. Responsible for more than 40% of the verification process Wrote comprehensive testcases in Perl that verify several features simultaneously · Tiber: SRP node. Partnership with CISCO . Main design and verification resource Designed the FIFO interface to the link layer device Designed the HDLC serial port ( Tx and Rx ) Involved in the top level integration Developed a feature rich, script driven SRP packet generator · Hudson 1: OC-192 (10Gbps) G.709 Forward Error Correction Participated in the verification

- En nove. 1999 [Celox Networks] CDI
Celox Networks ,

- En 2000 [Sprint] CDI
June St Louis , MO, USA Senior Verification Engineer Member of the Verification team. Participates in the design and development of the verification toolset to performa system level verification on a chipset which will be the core of a high performance IP edge service router. In charge of the hardware software (verilog/C) integration. Designed and developed the following: · verilog models that wrap up the chipset and models some board level components · board level overall model · library of components that communicate with the toolset via verilog PLI interface. · verilog/C memory models to speed-up the simulation. · Intelligent Bus snoopers · Interface with the other modules of the toolset · Bus functional models of POS (Packet Over SONET) April 1998 - Sprint ,

- En nove. 1999 [next] CDI
Overland Park , KS, USA Service Creation Environment Architect · Design and development of next generation service creation environment for Multi-media Multiparty Services . Project Leader. Project involves OO Design of a specialized CASE toolset dedicated to the creation of broadband multimedia services. The toolset includes: GUI based service components design based on ITU-ODL (Object Description Language) Integration with Telelogic SDT (ITU-SDL:Specification Description Language Tool) for Behavioral Description/Simulation/Verification. Parameterizable Advanced Code( C++ /Java) generation based on ODL, SDL and Service Architecture (Interactions). Integration with the TINA-C DPE (Distributed Processing Environment). · Design and Development of a Platform-Independent Service Creation Environment for narrowband services (voice mainly). Project aims to unify heterogeneous Service Creation Environments from different vendors into a unique SCE with the ability to deploy the produced service on any platform. The toolset includes: GUI based component (feature) design and implementation in Java Sample component library design. Fully graphic Service Creation Environment featuring graphic description of the created service. Flexible tool independent from the service features. Designed and Implemented in Java. Produces a service script coded in SDL. Integrated with Telelogic SDT for Simulation/Verification.

- En octo. 1993 CDI
­ University of Pierre and Marie Curie , Paris VI,

- En sept. 1997 [Teacher and Research] STAGE
Paris , France PhD Candidate, Teacher and Research Assistant. Teaching: · Taught VLSI implementation methodology and flow through a tutorial course of implementing an AMD 2901 datapath slice-processor. VHDL description and behavioral simulation Logic synthesis Test structure insertion Test pattern generation and coverage Place and route Pad ring · Taught practical digital specifications of MIPS R3000 Microprocessor and guided the students through the different methodology steps focusing on the VLSI implementation steps especially using a home grown datapath generator. · Supervised two Ms. CS final projects. · Supervised three Bs . CS and one Bs . EE final projects. · Some of the projects: Automatic routing scheme generation based on interval labeling (used in interconnection networks for parallel architectures); Masters Degree in Computer Science NDL (Network Description Language) subset parser; Bs . Degree in Computer Science Research: Member of the Computer Architecture group. Software Architect for European funded project MILE(OMI/MACRAME). Research on Interconnection Networks : · Design and Realization of a Simulation Environment for Performance Evaluation of Interconnections Networks : MILE. 30,000 lines of C-Code. Contains: A graphic Editor that allows the graphic edition of networks. A cycle-based Simulator using the communicating FSMs model. User- defined component libraries. The component definition is compliant with the object-oriented model. Work supported by the European Union (OMI/MACRAME). Performance Evaluation of several topologies: Multistage Interconnection Networks , Hypercubes, Meshes, etc... Performance evaluation of several buffering strategies for message crossbar-based switches (like ATM switches). Design of the Architecture of a Switching Circuit (16x16 crossbar). Work supported by the European Union (JESSI). Definition of a new theory for the verification of deadlock/livelock- freedom for routing algorithms. Design of an automatic labeling algorithm for indirect networks like Multistage Networks .

- En octo. 1992 CDI
University of Pierre and Marie Curie , Paris VI,

- En octo. 1993 CDI
Paris , France Master Student, Developed a portable RAM generator for ASIC designs. The generator included the development of: · The full software of the generator that takes care of the different generation variants and options available. · The full design of the RAM library cells which included: Schematic and behavioral Validation through Spice simulations Layout

- En déce. 1989 CDI
Ministry of Scientific Research,

- En octo. 1992 [Multiprocessor and Parallel] CDI
Algiers , Algeria Junior Researcher, Member of a team of four researchers. In charge of the design and implementation of a 32-bit RISC microprocessor: HRISC II. · Design of the Architecture and the Micro-architecture of a RISC Microprocessor: HRISC II. · Behavioral modeling and simulation of the micro-architecture · Full-custom VLSI implementation of the control path of HRISC II (+100K transistors) Technical Skills Multiprocessor and Parallel Architectures, RISC, CISC Computer Architecture (Microcontrollers), Superscalar, FPU, DSP , Multithreaded, Shared Design bus, Out-of-order execution Architecture: Intel x86, Pentium, Atmel Microcontrollers, ARM7, Microprocessors/ MIPS R2000/3000/4000, Rabbit Microcontrollers, Zilog Z80, Microcontrollers PowerPC. ISA, PCI, Compact PCI, PCI Express, HyperTransport, Infiniband, Standard Buses FibreChannel, RapidIO, USB, Firewire Spice, Eldo, Layout drawing VLSI Circuit Design Verilog, VHDL, Synthesis tools ( Synopsys ), Xilinx FPGA flow ASIC Flow · Telecommunication ATM: AAL2, AAL5, basic switching and MPLS · Protocols High speed Fiber: OC3/12/48/192/768 SONET/SDH, GFP (G.709) · TDM: ST- BUS /GCI, · Access : T1/E1/J1,T3/E3/J3, ADSL, VDSL · LAN : Ethernet : 10/100/1000/10G protocols, MII, RMII, SMII, S3MII, GMII, MACs, PHY negociation, VLAN tagging; WLAN · Link Layer : HDLC bit and byte protocol. · Embedded Buses: AMBA AHB, Wishbone · Serial: UART, SPI, I2C, I2S · Interfacing: ADC/DAC, Ultrasound/Infrared Sensor, LCD, VGA display device, GPS, IEEE 802.11 WLAN. C, C++ , Java, CORBA, ORBix, Unix, Windows XP , ITU/SDL. Software TCP/IP stack . TCP, HTTP, FTP, RTP, RTSP, RTCP, UDP, VoIP Networking Honors and Achievements · College of Computer Science and Engineering (CCSE) Senior Design Project

- En 2007 [AES] CDI
Supervision Award , June · Best Student Paper Award, IEEE Computer Society at PDCS'96, Dijon . · Seymour Cray 1st Prize Laureate from CRAY Computer Company as a member of Alliance designers team , 1994 ( see http://www-asim.lip6.fr/team/distinctions/cray94/ ) Languages · English Fluent · French Fluent · Arabic Fluent · Berber Good Publications 1. A. Bouhraoua and Mohammed E.S. El-Rabaa, "An Efficient Network-on-Chip Architecture Based on the Fat Tree (FT) Topology", Arabian Journal of Science and Engineering (AJSE), accepted for publication. 2. A. Bouhraoua, "Design Feasibility Study for a 500 Gbits/s AES Cypher/Decypher Engine", Arabian Journal of Science and Engineering , under review. 3. A. Bouhraoua, "Design Feasibility Study For a 500 Gbits/s AES Cypher/Decypher Engine", Proceedings of the International Conference on Microelectronics (ICM'06), 16-19 December 2006 , Dhahran , Saudi Arabia 4. A. Bouhraoua and Mohammed E.S. El-Rabaa, "An Efficient Network-on-Chip Architecture Based on the Fat Tree (FT) Topology", Proceedings of the International Conference on Microelectronics (ICM'06), 16-19 December 2006 , Dhahran , Saudi Arabia 5. A. Bouhraoua and Mohammed E.S. El-Rabaa, "A High-Throughput Network-on- Chip Architecture for Systems-on-Chip Interconnect," Proceedings of the International Symposium on System-on-Chip (SOC06), 14-16 November 2006 , Tampere , Finland. 6. A. Bouhraoua, B. Zerrouk et J. Faik, "Adaptive Message Routing for Compact Reconfigurable Router", ICECS'97, December 15th-17th 1997 , Cairo , Egypt 7. B. Zerrouk, A. Bouhraoua and F. Ilponse "Experimental Study of a Generic Router Architecture under MILE", IASTED'97, February 17-20th 1997 , Innsbruck , Austria. 8. B. Zerrouk and A. Bouhraoua, "MILE: An Open Environment for Interconnection Networks Performance Evaluation", Parallel and Distributed Computer Systems Conference (PDCS'96), September 25-27th 1996 , Dijon , France . 9. B. Zerrouk and A. Bouhraoua, "Evaluation of RCube Based Networks using

- En 1996 [MILE Software] CDI
MILE", Esprit-OMI/MACRAME Project Report, June 10. B. Zerrouk and A. Bouhraoua, " MILE Software Architecture Overview and

- En 1996 CDI
Principles", Esprit-OMI/MACRAME Project Report, May 11. B. Zerrouk, A. Bouhraoua and A. Greiner,"Defining a New Component for the

- En 1995 [Design and Implementation] CDI
MILE simulator", Esprit-OMI/MACRAME Project Report, March 12. A. Bouhraoua et A. Greiner, "A Portable SRAM Generator", International Conference on Microelectronics (ICM'94), September 19th-21st 1994 , Istanbul Turkey. 13. Y.I. El-Haffaf, A. Bouhraoua et A. Amari, " Design and Implementation of the Data- path of a 32-bits RISC Microprocessor: HRISC II", EURO-ASIC Conference, 1st- 5th June 1992 , Paris France . 14. Y.I. El-Haffaf, A. Bouhraoua et A. Amari, "Micro-Architecture Design and Implementation of HRISC II Microprocessor", EURO-ASIC Conference, 27th-31st May 1991 , Paris France . 15. A. Bouhraoua, A. Amari, A. Bellaouar, A. Afra et L. Sahli, "Micro-Architecture Design of HRISC II Microprocessor", Proceedings of the International Conference on Microelectronics (ICM'90), December 1990 , Damas , Syria. References Ghulam. M. Chaudhry Professor, Dept. of Computer and Electrical Engineering University of Missouri at Kansas City UMKC Phone: (816) 235-5214 Alaaeldin Amin Associate Professor, Dept. of Computer Engineering College of Computer Science and Engineering King Fahd University of Petroleum and Minerals Phone: +966-3-860-2862 Maamoun Seido Systems Engineer Zarklink Semiconductor Ottawa , Canada

- [Petroleum and Minerals]
Assistant Professor , Computer Engineering Department King Fahd University of Petroleum and Minerals Citizenship: Canadian